The present disclosure relates to an oscillation circuit and a test circuit, and more particularly to an oscillation circuit for measuring a leakage current, and a test circuit including the same.
In recent years, along with scale down of integrated circuits, a leakage current which is leaked from a transistor held in a non-conduction state has been increased, and an influence by the leakage current (for example, an increase in a power consumption in a phase of standby) has been disable to be ignored. For this reason, for example, in a phase of development of the integrated circuits, in a phase of release testing of the integrated circuits, and the like, it is necessary to measure the leakage currents in many cases. The leakage current largely differs every transistor depending on the kind and shape of the transistor within the integrated circuits, the dispersion of the quality in the phase of the manufacture, and the like. For this reason, it is required to locally measure the leakage current as much as possible in an area in which the transistors are integrated. For the purpose of locally measuring the leakage current, a dedicated test circuit is incorporated in a portion as an object of a measurement in many cases.
For example, there is proposed a test circuit using a Negative Metal-Oxide-Semiconductor (nMOS) transistor, a Positive MOS (pMOS) transistor, a comparator, and an inverter group. This test circuit, for example, is described in Japanese Patent Laid-Open No. 2010-43927. In this test circuit, the pMOS transistor and the nMOS transistor are connected in series with each other between a power source and the ground. The nMOS transistor is set to a non-conduction state by the grounding of both of a gate terminal and a source terminal. Also, each of output terminals of the nMOS transistor and the pMOS transistor connected in series is connected to an input terminal of the comparator. The inverter group serves to invert an output signal from the comparator and to feed the inverted output signal as an input signal back to the pMOS transistor.
When the input signal rises in the test circuit described above, in addition to the nMOS transistor, the pMOS transistor is also set to the non-conduction state. When the pMOS transistor and the nMOS transistor are both held in the non-conduction state, an electric potential at the output terminal of the nMOS transistor is gradually reduced due to the leakage current from the nMOS transistor. Also, when the electric potential at the output terminal of the nMOS transistor becomes lower than a reference electric potential, the output signal from the comparator falls.
A delay time from the fall of the input signal of the pMOS transistor to the fall of the output signal from the comparator is a time based on the leakage current from the nMOS transistor held in the non-conduction state. For this reason, the output signal from the comparator is changed at a frequency corresponding to that leakage current. A value of the leakage current from the nMOS transistor held in the non-conduction state is measured from the frequency. A leakage current from the pMOS transistor is also measured by a circuit having a symmetrical configuration.